Designing Combinational Circuits with PLA: Step-by-Step GuideA Programmable Logic Array (PLA) is a configurable device used to implement combinational logic by programming its AND (product) plane and OR (sum) plane. PLAs are useful for implementing multiple Boolean functions compactly and are an instructive bridge between fixed logic gates and more flexible devices like PALs and FPGAs. This guide walks through the entire process of designing combinational circuits with a PLA, from specification to implementation and optimization.
Overview: What a PLA Is and When to Use It
A PLA consists of:
- An input layer with true and complemented inputs available.
- A programmable AND plane that forms product terms (minterms or other AND combinations).
- A programmable OR plane that sums selected product terms to form output functions.
Use a PLA when you need to implement multiple Boolean functions that share common product terms or when learning programmable logic fundamentals. PLAs are ideal for medium-complexity combinational logic where explicit control over both product and sum terms is helpful. For very large designs or where reconfiguration speed and tool support matter, consider FPGAs.
Step 1 — Gather and Specify the Boolean Functions
Start with a clear specification: list all outputs and express each as a Boolean function of the available inputs. For example, suppose inputs are A, B, C and outputs are F1, F2, F3 specified by truth table or Boolean equations.
Example truth-table-based specification:
- Inputs: A, B, C
- Outputs:
- F1 = 1 for minterms m(1,3,5)
- F2 = 1 for minterms m(2,3,6,7)
- F3 = 1 for minterms m(0,4)
If functions are given as equations, ensure they are complete and unambiguous.
Step 2 — Derive Sum-of-Products (SOP) Expressions
Convert each output function to a Sum-of-Products (SOP) form (sum — OR of product — AND terms), since PLAs implement SOP naturally.
Methods:
- Read directly from the truth table (each minterm where function = 1 becomes a product term).
- Use Karnaugh maps (K-maps) or Quine–McCluskey algorithm to minimize SOP forms before mapping to the PLA.
- You may also derive non-minimal SOP first and minimize later across outputs to find shared product terms.
Example (from previous specification):
- F1 = A’ B’ C + A’ B C + A B’ C (minterms 1,3,5)
- F2 = A’ B C’ + A’ B C + A B C’ + A B C (minterms 2,3,6,7)
- F3 = A’ B’ C’ + A B’ C’ (minterms 0,4)
Step 3 — Minimize and Factor to Share Product Terms
One PLA advantage is reusing product terms across outputs. Minimization should therefore focus on:
- Reducing the number of distinct product terms.
- Factoring expressions to reveal common terms.
Techniques:
- Karnaugh maps across each function to find prime implicants; then select essential primes while preferring selection that covers multiple outputs.
- Use Espresso or similar logic minimization heuristics for larger designs.
- Algebraic factoring: e.g., if F1 = X·Y + X·Z and F2 = X·W, note X is common.
Example optimization:
- Suppose F1 and F2 both include A’ B C; keep a single product term P1 = A’·B·C and connect it to both F1 and F2 in the OR plane.
Step 4 — Determine Required Product Terms and PLA Size
List all unique product terms after minimization. Count them — that determines how many AND gate inputs (rows) you need in the AND plane. Check PLA device limits (number of product terms, number of inputs, number of outputs). Typical PLAs are specified as NxM where N = inputs, M = product terms or outputs — check vendor datasheet.
Example:
- Unique product terms might be: P0 = A’B’C’, P1 = A’B’C, P2 = A’BC’, P3 = A’BC, P4 = AB’C’, P5 = AB’C, etc.
- If after minimization you have 6 unique products and 3 outputs, you need a PLA with at least 6 product rows and 3 output columns.
Step 5 — Map Product Terms to the AND Plane
For each product term, specify which inputs are asserted, negated, or don’t-care in that row. The AND plane is programmed to connect input or inverted-input lines to a product row when that literal is required.
Representation convention:
- Use 1 for true input (connect normal input),
- 0 for complemented input (connect inverted input),
- – (dash) for don’t-care/no connection.
Example product-row table (for inputs A, B, C):
| Product | A | B | C |
|---|---|---|---|
| P0 | 0 | 0 | 0 |
| P1 | 0 | 0 | 1 |
| P2 | 0 | 1 | 0 |
| P3 | 0 | 1 | 1 |
| P4 | 1 | 0 | 0 |
| P5 | 1 | 0 | 1 |
Program the PLA’s AND-plane fuses or memory to produce these products.
Step 6 — Program the OR Plane Connections
For each output, connect the OR gate column to the rows (product terms) that should contribute to that output. In many PLAs this is done by programming a connection from product row to output column.
Example OR connections:
- F1: connect to P1, P3, P5
- F2: connect to P2, P3, P4, P5
- F3: connect to P0, P4
Ensure the PLA supports the fan-in (number of product terms feeding a single OR). If an output requires more product terms than the device supports, factor or rewrite to reduce terms or use multiple OR columns with additional logic.
Step 7 — Verify Logic Functionality (Truth Table / Simulation)
After mapping, verify correctness:
- Generate the truth table for the PLA mapping and compare with the specification.
- Use HDL (e.g., VHDL/Verilog) simulation or a PLA emulator if available.
- Check for hazards (static-1, static-0 hazards) in critical timing paths if outputs will drive asynchronous logic.
Example quick check: produce outputs for each input combination (000—111) and confirm match.
Step 8 — Timing, Fan-out, and Electrical Considerations
PLAs introduce propagation delay through the AND plane and OR plane. Consider:
- Propagation delays for AND and OR planes add up; use this when calculating overall combinational delay.
- Fan-out and loading: outputs feeding many inputs can require buffering.
- Power consumption increases with many programmed connections; sparse programming is lower power.
- For high-speed designs, consider minimizing number of plane connections in critical outputs or using registered outputs (flip-flops) to meet timing.
Step 9 — Testability and Implementation Notes
- Insert test vectors that exercise all product rows and output connections.
- Consider adding parity or built-in self-test in larger systems.
- For hardware PLAs, use specified programming tools and verify after programming with device readback (if supported).
- If implementing a PLA in an FPGA or ASIC standard-cell flow, map product-term generation to LUTs or AND-OR gate nets accordingly, and take advantage of synthesis tools to optimize.
Example: Full Walkthrough (A, B, C => F1, F2)
Specification (compact):
- F1 = Σm(1,3,5)
- F2 = Σm(2,3,6,7)
- F3 = Σm(0,4)
-
SOP (from minterms):
- F1 = A’B’C + A’BC + AB’C
- F2 = A’BC’ + A’BC + ABC’ + ABC
- F3 = A’B’C’ + AB’C’
-
Minimize and identify shared products:
- Notice A’BC appears in both F1 and F2 (m3).
- Products after grouping (example outcome): P0=A’B’C’, P1=A’B’C, P2=A’BC’, P3=A’BC, P4=AB’C’, P5=AB’C, P6=ABC’, P7=ABC
- You might be able to reduce with K-maps to fewer products (exercise left to reader).
-
Map products to AND-plane and OR-plane as shown previously.
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Verify truth table, simulate, check timing.
Alternatives and Practical Recommendations
- For small/simple designs, discrete gates or multiplexers may be simpler.
- For frequent updates or larger logic sets, prefer FPGAs for reconfigurability and tool support.
- When limited by product-term count, refactor logic to reduce distinct products or use hierarchical decomposition.
- Use automated minimizers (Espresso, synthesis tools) for large designs to find globally optimal sharing.
Closing Notes
PLAs are a clear, pedagogical tool for implementing combinational logic and are practical for moderate-size problems where explicit control of product and sum terms matters. The key steps are: obtain SOPs, minimize with sharing in mind, map product terms to the AND plane, connect the OR plane for outputs, and verify both function and timing.
If you give me a specific truth table or set of Boolean functions, I’ll perform the full minimization and produce the exact PLA AND/OR programming table and verification truth table.
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